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Digital Design & Computer Architecture — Cache Design, Management, and Tradeoffs

Source: YouTube — Onur Mutlu Lectures
Course: Digital Design and Computer Architecture, ETH Zürich, Spring 2026
Lecturer: Professor Onur Mutlu
Lecture: L23 — Cache Design, Management, and Tradeoffs
Course URL: safari.ethz.ch/ddca/spring2026/

TL;DR

Lecture 23 of Onur Mutlu's Digital Design and Computer Architecture course at ETH Zürich covers cache memory design principles: how caches are organised, the tradeoffs between capacity, associativity, block size, and latency, and management strategies for maximising hit rates. The lecture is part of a comprehensive Spring 2026 series spanning ISA, microarchitecture, memory hierarchy, and advanced topics.

Context

This course is ETH Zürich's undergraduate introduction to digital design and computer architecture. Professor Onur Mutlu is a leading researcher in computer architecture, memory systems, and hardware security, and his lectures are known for combining foundational principles with cutting-edge research insights.

Likely Topics Covered

Based on the lecture title "Cache Design, Management, and Tradeoffs," the lecture probably addresses:

  • Cache organisation: Direct-mapped, set-associative, fully-associative
  • Replacement policies: LRU, pseudo-LRU, random, adaptive policies
  • Write policies: Write-through vs. write-back, write-allocate vs. write-no-allocate
  • Performance tradeoffs: Capacity, associativity, block size, and their effects on miss rate, miss penalty, and hardware cost
  • Memory hierarchy design: How caches fit into the broader memory system

Key Takeaways

  1. Cache design is fundamentally about tradeoffs — no single organisation is optimal for all workloads
  2. Associativity reduces conflict misses but increases access latency and hardware complexity
  3. The memory hierarchy is the dominant factor in system performance — modern CPUs spend much of their time waiting for data
  4. Understanding cache behaviour is essential for writing performant code — data layout and access patterns directly impact cache hit rates